MESSAGE
| DATE | 2014-11-02 |
| FROM | Ruben Safir
|
| SUBJECT | Subject: [NYLXS - HANGOUT] [ruben@mrbrklyn.com: Re: Architecture Homework - Review Questions]
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TRUE OR FALSE
1. At a top level, a computer consists of CPU, memory, and I/O components.
True:
Comment and Notes:
At a top level, a computer consists of CPU (central processing unit),
memory, and I/O components, with one or more modules of each type. These
components are interconnected in some fashion to achieve the basic
function of the computer, which is to execute programs.
Thus, at a top level, we can characterize a computer system by describing:
(1) the external behavior of each component, that is, the data and
control signals that it exchanges with other components
(2) the interconnection structure and the controls required to manage
the use of the interconnection structure.
Virtually all contemporary computer designs are based on concepts
developed by John von Neumann at the Institute for Advanced Studies,
Princeton. Such a design is referred to as the von Neumann architecture
and is based on three key concepts:
??? Data and instructions are stored in a single read???write memory.
??? The contents of this memory are addressable by location, without
regard to the type of data contained there.
??? Execution occurs in a sequential fashion (unless explicitly modified)
from one instruction to the next.
With General Purpose (Van Neuman ) Hardware, input to the system is data
and control signals and output is a process. Programs are a series of
arithmetic or logical operations performed on some data. At each step
control signal(s) must be executed.
2.Program execution consists of repeating the process of instruction
fetch and instruction execution.
True: This is known as the FECHEX Cycle
The processing required for a single instruction is called an
instruction cycle.
3. An I/O module cannot exchange data directly with the processor.
False:
****Define Directly and please give me the reference****
Reasoning: As we say that the CPU can access data directly from memory
through the MAR, so to can it receive data directly from an I/O Module
via the I/OAR and stored int he I/O BR reference. If we say that the
CPU only is directly accessing its internal registers, then neither main
memory or I/O are directly accessed, but only CPU registries, and in
which case the answer to this question is TRUE because it can exchange
directly with the Processor.
4. A key characteristic of a bus is that it is not a shared transmission
medium.
True: And only one device on the bis can speak at a time, otherwise
communications become garbled. Buses communicate in parallel with words
comprised of several bits together.. A byte can be transmitted over 8
bus lines.
*********************************************************************
NOTE: Slide 27 or 52 needs to be entirely rewritten: As it reads is
actually incorrect and confusing:
Specifically the bullet points are wrong and in the notes the sentence:
"The data bus may consist of 32, 64,128 or even more separate lines, the
number of lines referred to as the "width" of the data bus"
is inconsistent with previous sentence.
Suggested rewording: The system bus typically consists of approximately
50 to 100 separate lines which are grouped into subunits of 32,64, 128
or even more of these separate lines to provide parallel communication
of word sizes across the system. This grouping size is called the "Data
Bus Width"
*********************************************************************
5. The method of using the same lines for multiple purposes is known as
time multiplexing.
True - but what is an ****Address validated control line****? This
section of the notes is written very poorly and if not coherent. It is
like two separate sections of notes have been disjointedly hammered
together. It just around and I'm having trouble teasing the conjoined
ideas apart.
6. Both sign-magnitude representation and twos complement representation
use the most significant bit as a sign bit
True
7. With asynchronous timing the occurrence of events on the bus is
determined by a clock.
False - maybe
8. It is extremely easy to convert between binary and hexadecimal notation.
Yes - maybe - easier than decimal
9. A key requirement for PCIe is high capacity to support the needs of
higher data rate I/O devices such as Gigabit Ethernet.
True
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